1. Field of the Invention
This invention is related to the field of direct memory access (DMA) controllers in computer systems.
2. Description of the Related Art
In a typical system that includes one or more processors, memory, and input/output (I/O) devices or interfaces, direct memory access (DMA) transfers are often used to transfer data between the I/O and the memory. In some systems, individual DMA circuitry is included in each I/O device or interface that uses DMA. In other systems, one or more I/O devices may share DMA circuitry.
Often, data is DMA transferred to memory to be processed by the processors, or data is created by the processors for DMA transferred to I/O. For example, packet data from a network interface, such as transport control protocol/internet protocol (TCP/IP) packets, are often received and processed. The processed packets may also be transmitted again, and the processors may also generate packets for transmission.
The “load” of processing the DMA data may be fairly large, and may impact the ability of the processors to execute other processing tasks. Some of the DMA processing may be fairly regular and well-defined. For example, packets may be encrypted and/or authenticated. Accordingly, received packets may have to be unencrypted by the processor and/or may have to be authenticated before other processing of the packets. Similarly, packets prepared for transmission may have to be encrypted and/or have authentication information (such as a hash of the packet data) generated. To the extent that the processing of DMA data presents an excessive load to the processor, performance in the system can be negatively impacted.
In some cases, hardware acceleration of some or all of the above tasks can be performed. In such cases, the data must generally be DMA transferred to the hardware accelerator, and the result data must be DMA transferred back to memory. A relatively complex task can involve multiple DMA transfers to and from various hardware accelerators. To ensure proper operation, a mechanism to control data flow between DMA transfers is needed.